1. Field of the Invention
The present invention relates to, e.g., a MOS semiconductor device and a method of manufacturing the same and, more particularly, to a MOS semiconductor device having an improved source/drain region and to a method of manufacturing the same.
2. Background of the Invention
Recently, micropatterning and integration technologies for semiconductor devices are advancing. However, micropatterning of semiconductor devices is not based on scaling of a constant electric field, and the electric field in a semiconductor device tends to increase as the device is more finely micropatterned. Especially, in a MOS transistor, degradation in characteristics due to hot carriers is a serious problem.
As a preferable method of suppressing generation of hot carriers, a method of forming a source/drain having a so-called LDD structure is proposed, in which the first diffusion layer (LDD region) having a shallow junction and the second diffusion layer having a junction deeper than the first diffusion layer are made to partially overlap to form an impurity diffusion layer. According to the LDD structure, the concentration gradient at the drain end becomes gradual because of the relatively lightly doped LDD region, resulting in relaxation of field concentration. This decreases the substrate current, thereby suppressing generation of hot carriers.
The LDD region has a concentration for minimizing the substrate current at the drain end. This optimum concentration tends to gradually become high as the semiconductor device is more finely micropatterned. However, an increase in the concentration of the LDD region prompts the short channel effect, resulting in a decrease in threshold voltage or an increase in leakage current (punch through).
To suppress the short channel effect, the junction of the source/drain region may be made shallow. More specifically, the acceleration energy for ion-implanting impurities into the semiconductor substrate may be lowered, or annealing in device formation may be performed at a low temperature or for a short time. The shallow junction of the source/drain region also contributes to suppressing generation of hot carriers.
However, when the junction of the source/drain region is made shallow, the sheet resistance in this region increases, and the parasitic resistance also increases. The increase in parasitic resistance causes not only degradation in driving capability of the semiconductor device but also a decrease in switching speed of the logic circuit or a decrease in operation margin of the semiconductor storage device (memory), resulting in degradation in characteristics.
To suppress the increase in parasitic resistance due to the shallow junction, a so-called raised source/drain structure is proposed (S. S. Wong et al., IEDM Technology Digest p. 634, 1984), in which the source/drain region is formed by raising it from the semiconductor substrate surface. A method using both the raised source/drain structure and the LDD structure is also proposed (J. R. Pfiester et al., IEDM Technology Digest p. 885, 1992). Even in these methods, however, if annealing in device formation is the same as in the conventional method, the degree of thermal diffusion does not change, and the junction depth from the semiconductor substrate surface does not change either, so the above problem cannot be solved.
Japanese Patent Laid-Open No. 8-78671 discloses a method of implanting impurity ions through an ion implantation pad made of an insulating film or a conductive film to enable formation of a shallow junction by conventional annealing. In this method, dispersion due to ion scattering is increased so that the impurity distribution on the semiconductor substrate surface has a low peak and a large dispersion. However, in this method, the use of an insulating film as the ion implantation pad only enables forming of a shallow junction and it and cannot suppress the increase in parasitic resistance. When a conductive film is used as the ion implantation pad, the impurity concentration in the conductive film is lowered, so the sheet resistance of the conductive film cannot be sufficiently lowered. More specifically, when impurities are ion-implanted into the conductive film at a dose for sufficiently decreasing the sheet resistance, the impurities are diffused by subsequent annealing, so the shallow junction can hardly be formed.
Japanese Patent No. 2554055 discloses a method of implanting ions for forming a low-resistance polysilicon film. In this method, ion implantation is performed so that the impurity concentration is maximized immediately below the surface of the polysilicon film, and the polysilicon film does not become amorphous due to the impurities on the lowermost surface of the polysilicon film.
In fact, with ion implantation performed only once, the resistance of the polysilicon film can hardly be sufficiently lowered. Although this method contributes to reducing the contact resistance to the source/drain region, the effect for making the source/drain junction shallow is small.
It is an object of the present invention to provide a semiconductor device in which the junction depth of an impurity diffusion layer is made shallow to suppress generation of hot carriers or the short channel effect, and the impurity diffusion layer has a low resistance. The invention also relates to a method of manufacturing a device of the type.
It is another object of the present invention to form a low-resistance lead-out electrode connected to an impurity diffusion layer to suppress an increase in electrical resistance at the interface between the lead-out electrode and the impurity diffusion layer and to also suppress an increase in electrical resistance at the interface between the lead-out electrode and a wiring layer formed on the lead-out electrode.
According to an aspect of the present invention, there is provided a semiconductor device comprising an impurity diffusion layer formed in a semiconductor substrate, and a wiring film connected to the impurity diffusion layer, wherein the wiring film contains impurities, a diffusion profile of the impurities in an entire region of the wiring film in the direction of thickness has at least two impurity concentration inflection points above an interface between the wiring film and the impurity diffusion layer. The impurity concentration inflection points are present in about a lower ⅓ range of a thickness of the wiring film and about an upper ⅓ range of the thickness of the wiring film.
According to another aspect of the present invention, there is provided a semiconductor device comprising a first conductive film buried in an insulating film in an element formation region demarcated on a semiconductor substrate, a pair of impurity diffusion layers formed in a surface region of the semiconductor substrate on both sides of the first conductive film, and second conductive films seperated from each other to be connected respectively to each of the impurity diffusion layers in the semiconductor substrate on both sides of the first conductive film, and containing impurities, wherein a diffusion profile of the impurities in an entire region of the second conductive film in the direction of thickness has at least two impurity concentration inflection points.
According to still another aspect of the present invention, there is provided a semiconductor device comprising an impurity diffusion layer formed in a semiconductor substrate, and a wiring film connected to the impurity diffusion layer, wherein the wiring film contains impurities, a diffusion profile of the impurities in an entire region of the wiring film in the direction of thickness has at least one impurity concentration inflection point above an interface between the wiring film and the impurity diffusion layer, and the impurity concentration inflection point is present in about a lower ⅓ range of a thickness of the wiring film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising an impurity diffusion layer formed in a semiconductor substrate, and a wiring film connected to the impurity diffusion layer, wherein the wiring film contains impurities, and a diffusion profile of the impurities in an entire region of the wiring film in the direction of thickness has at least two impurity concentration inflection points.
According to still another aspect of the present invention, there is provided a semiconductor device comprising an impurity diffusion layer formed in a semiconductor substrate, a wiring film connected to the impurity diffusion layer, and a silicide film formed on the wiring film, wherein the wiring film contains impurities, a diffusion profile of the impurities in an entire region of the wiring film in the direction of thickness has at least one impurity concentration inflection point above an interface between the wiring film and the impurity diffusion layer, and the impurity concentration inflection point is present in about an upper ⅓ range of a thickness of the wiring film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising an impurity diffusion layer formed in a semiconductor substrate, and a wiring film connected to the impurity diffusion layer, wherein the wiring film contains impurities, a diffusion profile of the impurities in an entire region of the wiring film in the direction of thickness has n (n is An integer, nxe2x89xa72) different impurity concentration inflection points, and the impurity concentration inflection points are present in different ranges each corresponding to about 1/n of a thickness of the wiring film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a thin film as a prospective conductive film, an impurity concentration peak is formed near at least one of an upper end face and lower end face of the thin film, and a conductive film connected to the end face close to a region where the impurity concentration peak is formed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising 1) a first step of sequentially forming a first insulating film, a first conductive film, and a second insulating film in an element formation region demarcated on a semiconductor substrate and patterning the first insulating film, the first conductive film, and the second insulating film; 2) a second step of forming a third insulating film on a side surface of at least the first conductive film; 3) a third step of forming a silicon film on the semiconductor substrate to cover the second and third insulating films; 4) a fourth step of doping first impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film so that a concentration peak is formed near a lower surface of the silicon film; 5) a fifth step of doping second impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film so that a concentration peak is formed near an upper surface of the silicon film, 6) a sixth step of dividing the silicon film at least on the second insulating film, and 7) a seventh step of annealing the semiconductor substrate to diffuse the first impurities into the semiconductor substrate, thereby forming a pair of impurity diffusion layers each having a shallow junction, and diffusing the first and second impurities in the silicon film, thereby forming a second conductive film.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a transistor having a gate and a pair of impurity diffusion layer 3 in a semiconductor substrate, comprising a first step of covering the gate with an insulating film, a second step of forming a silicon film constituting part of a lead-out electrode connected to the impurity diffusion layer to cover the semiconductor substrate over an upper portion of the insulating film, a third step of polishing the silicon film until the upper portion of the insulating film is exposed, a fourth step of doping first impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film such that a concentration peak is formed near a lower surface of the silicon film, a fifth step of doping second impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film such that a concentration peak is formed near an upper surface of the silicon film, and a sixth step of annealing the semiconductor substrate to diffuse the first impurities into the semiconductor substrate, thereby forming the pair of impurity diffusion layers each having a shallow junction, and diffusing the first and second impurities in the silicon film, thereby forming the lead-out electrode.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step of forming a thin film as a prospective conductive film, a second step of doping impurities into a portion near an upper surface of the thin film, a third step of forming a refractory metal film on the thin film, and a fourth step of annealing the thin film and the refractory metal film to cause the thin film and the refractory metal film to react each other.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step of sequentially forming a first insulating film, a first conductive film, and a second insulating film in an element formation region demarcated on a semiconductor substrate and patterning the first insulating film, the first conductive film, and the second insulating film, the second step of forming a third insulating film on a side surface of at least the first conductive film, a third step of forming a silicon film on the semiconductor substrate to cover the second and third insulating films, a fourth step of doping first impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film such that a concentration peak is formed near a lower surface of the silicon film, a fifth step of doping second impurities having a conductivity type opposite to that of the semiconductor substrate into the silicon film such that a concentration peak is formed near an upper surface of the silicon film, a sixth step of dividing the silicon film at least on the second insulating film, a seventh step of forming a refractory metal film to cover at least part of the silicon film, and a eighth step of annealing the semiconductor substrate to diffuse the first impurities into the semiconductor substrate, thereby forming a pair of impurity diffusion layers each having a shallow junction, diffusing the first and second impurities in the silicon film, thereby forming a second conductive film, and converting the refractory metal film into a silicide.
In the present invention, the silicon film is formed on the semiconductor substrate on both sides of the first conductive film, and impurities are doped into the silicon film twice to form the second conductive film. For the first time, impurities are doped at a relatively low concentration such that the concentration peak is formed near the lower surface of the silicon film. For the second time, impurities are doped at a relatively high concentration such that the concentration peak is formed near the upper surface of the silicon film. The relatively low-concentration impurity distribution formed by the first impurity doping is diffused into the semiconductor substrate by subsequent annealing to form, e.g., a source/drain region as an impurity diffusion layer having a lightly doped shallow junction. On the other hand, the relatively high-concentration impurity distribution formed by the second impurity doping is diffused into the silicon film by subsequent annealing to form the second conductive film diffused by the high-concentration impurities. When the second impurity doping is performed such that the impurities are distributed in a sufficiently shallow portion near the surface of the silicon film, formation of the impurity diffusion layer having a lightly doped shallow junction is not impeded by subsequent annealing. Therefore, the impurity diffusion layer having a shallow junction can be formed to suppress generation of hot carriers or the short channel effect. In addition, the resistance of the impurity diffusion layer can be lowered.
In the present invention, the high-concentration impurity diffusion layer is formed near the upper surface of the silicon film by ion implantation. After the refractory metal film is formed on the silicon film, annealing is performed to convert the refractory metal film into a silicide. Even when the impurities in the silicon film are diffused to the refractory metal film side by annealing, the impurity concentration near the interface between the silicon film and the refractory metal film can be kept high. Therefore, the refractory metal film as a silicide film can be formed on the silicon film while keeping the resistance of the silicon film low.
According to the present invention, the junction depth of the impurity diffusion layer in the semiconductor device can be made shallow to suppress generation of hot carriers or the short channel effect. In addition, the resistance of the impurity diffusion layer can be lowered.